Semiconductor circuit including electrostatic discharge circuit having protection element and trigger transistor

ABSTRACT

A semiconductor circuit includes a first pad for a first power source, a second pad for a second power source, a third pad for an input/output signal, a protection element arranged between the first pad and the third pad, and a transistor functioning as a trigger element for use in passing a trigger current through the protection element. The transistor includes source connected to the third pad, a gate and a backgate commonly connected to the second pad.

The present Application is a Divisional Application of U.S. patentapplication Ser. No. 12/071,766, filed on Feb. 26, 2008.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon, claims the benefit of priority of, andincorporates by reference the contents of Japanese Patent ApplicationNo. 2007-057165 filed on Mar. 7, 2007.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a semiconductor circuit and more particularlyto a semiconductor integrated circuit on which an electrostaticdischarge (ESD) protection circuit for use in preventing damage to aninternal circuit caused by an ESD and application of surges isinstalled.

2. Description of Related Art

On the semiconductor integrated circuit is installed an ESD protectioncircuit for use in protecting an internal circuit against a surgeapplied to input/output pads. One of the well-known circuit topologiesin the ESD protection circuit is a circuit topology using a siliconcontrolled rectifier (SCR). The ESD protection circuit using the SCR hasan advantage that a discharging capability for performing an activeoperation is high when the surge is inputted, and this circuit is thuswidely used.

The ESD protection circuit using the SCR is typically constituted by aSCR and a trigger element connected to the gate of the SCR. One of theelements to be used as the trigger element is a PMOS transistor. Forexample, Japanese Patent Laid-Open Application No. 2003-318265 disclosesan ESD protection circuit having a configuration in which the PMOStransistor is connected to the gate of P gate-type SCR (refer to FIG.1). The ESD protection circuit in FIG. 1 is constituted by the SCR andthe PMOS transistor 105. Anode of the SCR is connected to an I/O pad102, and its cathode is connected to VSS pad 103. The gate of the SCR isconnected to a drain of the PMOS transistor 105. The gate of the PMOStransistor 105 is connected to a VDD pad 101, and its source andbackgate are connected to the I/O. pad 102. Further, although FIG. 2 ofJapanese Patent Laid-Open Application No. 2003-318265 illustrates theESD protection circuit where the input circuit 104 is connected to theVDD pad 101, this illustration would be an erroneous expression.

In addition, as the trigger element, the NMOS transistor may also beused. Japanese Patent Laid-Open Application No. 2003-203985 and itscorresponding U.S. Patent Application, i.e. U.S. Pat. No. 6,545,321disclose an ESD protection circuit having a configuration in which theNMOS transistor acting as a trigger element is connected to the gate ofN-gate type SCR. In addition, Japanese Patent Laid-Open Application No.2006-303110 discloses a configuration in which the PMOS transistor isused as the trigger element and also the NMOS transistor is used.

In addition, as already been disclosed in the reference: M. Mergens etal., IEEE raps. Device Materi. Reliab. vol. 5, no. 3, pp. 532-542,September 2005, it is also possible to use diodes connected in series asthe trigger element. FIG. 2 shows a configuration of the ESD protectioncircuit having such a configuration as above. The ESD protection circuitshown in FIG. 2 is constituted by the SCR and the diodes 106 connectedin series. Anode of the SCR is connected to the I/O pad 102 and itscathode is connected to the VSS pad 103. As the trigger element, thediodes 106 connected in series in a forward direction from the gate ofthe SCR toward the VSS pad 103 are used.

One requirement applied to the ESD protection circuit consists in thefact that a leakage current at the I/O pad is low during normaloperation. That is, under a condition in which the VDD pad is kept atthe power supply voltage level VDD and the VSS pad is kept at the groundlevel VSS, it is preferable that the leakage current flowed from the I/Opad through the ESD protection circuit is low. The leakage current inthe I/O pad is important in reduction of a consumption current in thesemiconductor integrated circuit.

Another requirement applied to the ESD protection circuit consists in alow trigger voltage in which the SCR starts to operate during ESD stresscondition, in particular, a low trigger voltage when an ESD stress ofpositive voltage for the VSS pad is applied to the I/O pad. A circuittopology using the SCR shows a tendency that the trigger voltage becomeshigh when the ESD stress of positive voltage for the VSS pad is appliedto the I/O pad, in particular. If the trigger voltage is high, it showsa certain problem because an internal circuit may be damaged.

However, the aforementioned ESD protection circuit cannot satisfy theseboth requirements. For example, although the ESD protection circuitshown in FIG. 1 can reduce the trigger voltage of the SCR, it cannotreduce the leakage current of the I/O pad. A reason why this occursconsists in the fact that a value of leakage current in the I/O pad 102when “High” level (i.e. a power supply voltage level VDD) is applied tothe I/O pad 102 is determined by an off-leakage current I_(OFF) of thePMOS transistor 105. In this case, the off-leakage current I_(OFF) is adrain-source current I_(DS) when both a gate-source voltage V_(GS) and abackgate-source voltage V_(BS) of the PMOS transistor 105 are 0V. Withsuch a configuration as described above, the leakage current at the I/Opad 102 cannot be reduced to a value less than the off-leakage currentI_(OFF) of the PMOS transistor 105.

Even the ESD protection circuit in FIG. 2 can reduce the trigger voltageof the SCR by reducing the number of the diodes 106. However, theleakage current at the I/O pad 102 is high because the diodes 106 areconnected in a forward direction toward the ground line (the powersource line connected to the VSS pad 103).

B. Keppcns et al., EOS/ESD Symposium Proceedings, 4B.7, 2004 disclosethe ESD protection circuit for satisfying aforementioned both tworequirements. FIG. 3A shows a circuit diagram indicating a configurationof the ESD protection circuit disclosed in this document. The ESDprotection circuit in FIG. 3A is provided with N-gate type SCR. Theanode of the SCR is connected to the I/O pad 102 and its cathode isconnected to the VSS pad 103. A gate G2 of the SCR is connected to theVDD pad 101 through a resistor R2.

FIG. 3B is a view for showing a sectional structure of the semiconductorintegrated circuit for realizing the ESD protection circuit shown inFIG. 3A. The ESD protection circuit shown in FIG. 3A is integrated atthe P-type substrate 111 having N-well 112 formed the rein. The P-typesubstrate 111 is formed with P⁺ region 113 and N⁺ region 114, and the P⁺region 113 and N⁺ region 114 are connected to the VSS pad 103. In thiscase, P⁺ region is a region where P-type impurities are doped under ahigh concentration and N⁺ region is a region where N-type impurities aredoped under a high concentration. In addition, an N-well region 112 isformed with a P⁺ region 115 and an N⁺ region 116. The P⁺ region 115 isconnected to the I/O pad 102 and the N⁺ region 116 is connected to theVDD pad 101. The P⁺ region 115, N-well 112, P-type substrate 111 and N⁺region 114 act as a SCR (having PNPN structure). The P⁺ region 113, N⁺region 114, P⁺ region 115, and N⁺ region 116 are separated from eachother by field oxide films 117. The resistor of the P-type substrate 111acts as a resistor element R1 in FIG. 3A and a resistor of the N-well112 acts as a resistor element R2.

A leakage current at the I/O pad 102 is less in the ESD protectioncircuit of FIG. 3A because the gate G2 of the SCR is clamped at thepower source voltage level VDD during its normal operation. In addition,when the ESD stress of positive voltage is applicd to the I/O padagainst the VSS pad 103, the VDD pad 101 is of a floating condition, sothat a forward biasing may easily be applied between the anode and gateG2 of the SCR. Accordingly, the ESD protection circuit in FIG. 3A canreduce the trigger voltage of the SCR.

However, the ESD protection circuit in FIG. 3A shows a problem that a pnjunction between the P⁺ region 115 and N-well 112 may easily be damagedwhen an ESD stress of negative polarity for the VDD pad 101 is appliedagainst the I/O pad 102. This problem is particularly serious when anarea of the pn junction between the P⁺ region 115 and N-well 112 isreduced so as to reduce a parasitic capacitance of the SCR. Accordingly,the ESD protection circuit in FIG. 3A cannot be a practical one.

As described above, it is believed that it has not been well known inthe art that such a practical technology as one satisfying the tworequirements of reduction of the leakage current at the I/O pad underthe normal operating state and reduction of trigger voltage when the ESDstress of positive voltage is applied to the I/O pad with respect to theVSS pad.

SUMMARY OF THE INVENTION

The semiconductor circuit of the present invention comprises exemplarilya VDD pad, an I/O pad, a VSS pad, a protection element arranged betweenthe I/O pad and the VSS pad, and a PMOS transistor acting as a triggerelement for flowing a trigger current in the protection element. Thegate and backgate of the PMOS transistor are connected to the VDD pad.The aforementioned protection element is constituted such that thepotential at the source of the PMOS transistor is lower than thepotential of the I/O pad due to a voltage drop generated at theprotection element when the potentials of the VDD pad and I/O pad arekept at the power supply voltage level.

In such a semiconductor circuit having such a configuration as describedabove, it is possible to reduce the sub-threshold current flowingthrough the PMOS transistor under the normal operating state. A reasonwhy this state can be attained consists in the fact that the gate-sourcevoltage of the PMOS transistor becomes a positive voltage because thepotential of source of the PMOS transistor is lower than the potentialof the VDD pad due to a voltage drop generated at the protectionelement. Thus, the semiconductor circuit of the present invention canreduce the leakage current at the I/O pad.

In addition, the semiconductor circuit of the present invention has anadvantage that a trigger voltage when the ESD stress of a positivevoltage for the VSS pad is applied to the I/O pad is low. In the casethat the ESD stress of a positive voltage for the VSS pad is applied tothe I/O pad, the VDD pad is kept floating to cause the gate and backgateof the PMOS transistor to become a floating state. In addition, the ESDstress of a positive voltage for the VSS pad is applied to the I/O padto cause the source potential of the PMOS transistor to become apositive potential for the VSS pad. Accordingly, the potential of theI/O pad required for lowering the gate-source voltage of the PMOStransistor than a threshold voltage V_(TH) is low. Accordingly, thetrigger voltage when the ESD stress of a positive voltage for the VSSpad is applied to the I/O pad is reduced.

Preferably, a SCR is used as the protection element. In this case, theanode of the SCR is connected to the I/O pad, its cathode is connectedto the VSS pad and its gate is connected to the source of the PMOStransistor.

According to the present invention, it is possible to provide an ESDprotection circuit having a low leakage current under a normal operatingstate and having a low trigger voltage at the time of application of theESD stress.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other exemplary aspects, advantages and features of thepresent invention will be more apparent from the following descriptionof certain exemplary embodiments taken in conjunction with theaccompanying drawings, in which:

FIG. 1 is a circuit diagram for showing an example of a configuration ofthe related art ESD protection circuit;

FIG. 2 is a circuit diagram for showing another example of aconfiguration of the related art ESD protection circuit;

FIG. 3A is a circuit diagram for showing a still further example of aconfiguration of the related art ESD protection circuit;

FIG. 3B is a sectional view for realizing the ESD protection circuit inFIG. 3A;

FIG. 4A is a circuit diagram for showing a configuration of the ESDprotection circuit of a first embodiment of the present invention;

FIG. 4B is a sectional view for showing a sectional structure of a SCRincluded in the ESD protection circuit of FIG. 4A;

FIG. 5A is a graph for indicating an operating characteristic of thePMOS transistor, in particular, a relation between the gate-sourcevoltage V_(GS) and the drain current I_(D);

FIG. 5B is a graph for indicating an operating point of a leakagecurrent under a normal operating state in the ESD protection circuit ofFIG. 4A;

FIG. 6 is a view for indicating an equivalent circuit for the ESDprotection circuit of the first embodiment when the ESD stress of apositive polarity is applied to the I/O pad with respect to the VSS pad;

FIG. 7 is a view for indicating an equivalent circuit for the ESDprotection circuit of the first embodiment when the ESD stress of apositive polarity for the VDD pad is applied to the I/O pad;

FIG. 8A is a circuit diagram for indicating a configuration of the ESDprotection circuit of a second embodiment of the present invention; and

FIG. 8B is a sectional view for indicating a sectional structure of aSCR included in the ESD protection circuit of FIG. 8A.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS First Embodiment

FIG. 4A is a circuit diagram for showing a configuration of the ESDprotection circuit of a first embodiment of the present invention. TheESD protection circuit of the first embodiment comprises an N-gate typeSCR 1, the PMOS transistor 2 for a trigger and a backward diode 3.

The SCR 1 acts as a protection element for discharging a loadaccumulated in the I/O pad 5 when the ESD stress (or surge) of apositive polarity is applied to the I/O pad 5. In FIG. 4A, the SCR 1 isequivalently expressed as it comprises NPN transistor Q1 and PNPtransistor Q2. The anode of the SCR 1 is connected to the I/O pad 5 andits cathode is connected to the VSS pad 6. In this case, the I/O pad 5is a pad connected to a signal line 22 for inputting or outputting asignal in respect to an internal circuit 8, and the VSS pad 6 is a padto which the ground potential VSS is supplied from an external unit. TheVSS pad 6 is connected to a VSS power supply line 23.

The PMOS transistor 2 for a trigger has a function for turning on theSCR 1. The PMOS transistor 2 for a trigger has its source connected tothe gate of the SCR 1, its drain connectcd to the VSS power supply line23 (i.e. VSS pad 6) and its gate and backgate connected to the VDD pad4. In this case, the VDD pad 4 is a pad to which the power supplypotential VDD is supplied from an external unit. The VDD pad 4 isconnected to the VDD power supply line 21.

The backward diode 3 has a function for discharging a load accumulatedin the VSS pad 6 when the ESD stress (or surge) of a positive polarityfor the I/O pad 5 is applied to the I/O pad with respect to the VSS pad6. The cathode of backward diode 3 is connected to the I/O pad 5 and theanode of backward diode 3 is connected to the VSS pad 6.

Supplying of the power supply voltage to the internal circuit 8 iscarried out by the VDD power supply line 21 and the VSS power supplyline 23. A power clamp diode 7 is connected between the VDD power supplyline 21 and the VSS power supply line 23. The power clamp diode 7 mayact as a protection element between the VDD pad 4 and the VSS pad 6.

FIG. 4B is a view for showing a sectional structure of the SCR 1. TheSCR 1 is integrated on a P-type substrate 11 having an N-well 12 formedthereon. The P-type substrate 11 is formed with P⁺ region 13 and N⁺region 14, and the P⁺ region 13 and N⁺ region 14 are connected to theVSS pad 6. N⁺ region 14 may act as a cathode for the SCR 1. In addition,P⁺ region 15 and N⁺ region 16 are formed in the N-well 12. P⁺ region 15is connected to the I/O pad 5, and N⁺ region 16 is connected to thesource of the PMOS transistor 2 for a trigger. P⁺ region 15 acts as theanode of the SCR and N⁺ region 16 acts as a gate. P+ region 13, N⁺region 14, P⁺ region 15 and N⁺ region are separated from each other bythe field oxide film 17. A resistor R_(PSUM) of P-type substrate 11 actsas a resistor for applying a bias to NPN transistor Q1, and a resistorR_(NW) of N-well 12 acts as a resistor connected between the gate of theSCR 1 and the base of PNP transistor Q2.

The ESD protection circuit having such a configuration as above enablesa leakage current at the I/O pad 5 to be reduced under a normaloperating state, and also enables the trigger voltage to be reduced whenthe ESD stress of a positive voltage for the VSS pad 6 is applied to theI/O pad 5. A reason why such an advantage as above will be described indetail.

At first, a principle of reduction in leakage current of the I/O pad 5under a normal operating state will be described. A reason why theleakage current at the I/O pad 5 is reduced under the normal operatingcondition consists in the fact that the potential at the source of thePMOS transistor for a trigger is kept at a lower potential than that ofthe gate and the backgate of the PMOS transistor 2 for a trigger (evenif the I/O pad 5 is a power supply voltage level VDD) due to a voltagedrop at the pn junction between the anode and the gate of the SCR 1. Theleakage current at the I/O pad 5 under the normal operating state ismainly determined by a sub-threshold current at the PMOS transistor 2for a trigger (since currents flowing in the SCR 1 and the backwarddiodes 3 are quite low as compared with the current flowing at the PMOStransistor 2 for a trigger, it can be ignored). The sub-thresholdcurrent flowing at the PMOS transistor 2 for a trigger is decreased in amanner of an exponential function as the gate-source voltage V_(GS) andthe gate-backgate voltage V_(BS) of the PMOS transistor 2 for a triggerare increased. In this case, the gate-source voltage V_(GS) and thegate-backgate voltage V_(BS) of the PMOS transistor 2 are the potentialof the gate and the potential of the backgate, respectively, when thesource is applied as a reference value. Under the normal operatingstate, the gate and the backgate of the PMOS transistor for a triggerare kept at the power source voltage level VDD and in turn the source ofthe PMOS transistor 2 for a trigger is kept at a lower potential thanthat of the power source voltage level VDD only by a value of thevoltage drop of the anode-gate (i.e. the emitter/base junction of PNPtransistor Q2) of the SCR 1. In other words, the gate-source voltageV_(GS) and the gate-backgate voltage V_(BS) of the PMOS transistor 2 fora trigger are increased only by an amount corresponding to the voltagedrop between the anode-gate of the SCR 1. Accordingly, the ESDprotection circuit of the embodiment can extremely decrease thesub-threshold current flowing at the PMOS transistor 2 for a trigger,i.e. a leakage current at the I/O pad 5.

The reduction in the leakage current at the ESD protection circuit ofthe embodiment would be understood more clearly if it is compared withthat of the ESD protection circuit shown in FIG. 1. In the ESDprotection circuit in FIG. 1, the leakage current of the I/O pad 102under the normal operating state coincides with the sub-thresholdcurrent of the PMOS transistor 105 when the gate-source voltage V_(GS)and the backgate-source voltage V_(BS) are 0 V. In turn, in the ESDprotection circuit of the embodiment is quite low as compared with thesub-threshold current flowing at the PMOS transistor 105 in the ESDprotection circuit in FIG. 1.

FIG. 5A and FIG. 5B are graphs for showing a more detailed illustrationof a principle in which a leakage current at the I/O pad 5 is reducedduring normal operation. In the following description, a “High” levelsignal is inputted to the I/O pad 5. That is, it should be noted about aconsideration in the case that the potential of the I/O pad 5 is a powersupply voltage level VDD.

FIG. 5A is a graph for showing a dependency of a drain current I_(D) (acurrent flowing into the drain of the PMOS transistor) of the PMOStransistor on the gate-source voltage V_(GS). In the case that thegate-source voltage V_(GS) is lower than the threshold voltage V_(PTH)(<0V), the PMOS transistor is kept in a high reversing region (asaturation region) and then a saturated drain current I_(D) flows. Asthe gate-source voltage V_(GS) becomes higher than the threshold voltageV_(PTH), the PMOS transistor becomes a weak reversing region and thedrain current I_(D) is decreased in an exponential function manner asthe gate-source voltage V_(GS) is increased. In the weak reversingregion, the sub-threshold current I_(S) determines the drain currentI_(D). As the gate-source voltage V_(GS) becomes further high (in FIG.5A, as it becomes higher than a potential V_(X) (>0)), the drain currentI_(D) is governed not by the sub-threshold current I_(S) but by thebackward current I_(B) of the drain/backgate junction and the gateoxidization film tunnel current I_(G). In this case, noticing only thesub-threshold current I_(S), a voltage where the sub-threshold currentI_(S) starts to flow is defined as V_(STH).

In addition, the drain current I_(D) of the PMOS transistor is alsoinfluenced by the backgate-source voltage V_(BS). More practically, whenthe backgate-source voltage V_(BS) is increased from 0V, the draincurrent I_(D) of the PMOS transistor is decreased. That is, when thebackgate-source voltage V_(BS) is increased, the sub-threshold currentI_(S) of the PMOS transistor is lowered.

In the circuit configuration of the ESD protection circuit in thisembodiment, since the gate and the backgate of the PMOS transistor for atrigger are connected to a VDD Power source line 21, the backwardcurrent I_(B) and the gate oxidization film tunnel current I_(G)contributes as a leakage current between the VDD pad 4 and the VSS pad6, but does not contribute to the leakage current of the I/O pad 5.Accordingly, only the sub-threshold current I_(S) of THE PMOS transistor2 for a trigger contributes to the leakage current of the I/O pad 5.

FIG. 5B is a graph for showing operating points of PNP transistor Q2 ofthe SCR 1 and the PMOS transistor 2 for a trigger at the time of normaloperating state. X-axis denotes a potential of N-well 12 (i.e. thedrain-source voltage of the PMOS transistor 2 for a trigger) and Y-axisdenotes a base current I_(PNP) of PNP transistor Q2 and a sub-thresholdcurrent I_(PMOS) of the PMOS transistor 2 for a trigger.

Operating points of PNP transistor Q2 and the PMOS transistor 2 for atrigger become the crossing point between the graph of the base currentI_(PNP) and the graph of the sub-threshold current I_(PNP) because thebase current I_(PNP) of PNP transistor Q2 and the sub-threshold currentI_(PMOS) of the PMOS transistor 2 for a trigger are coincided to eachother during normal operation. That is, during normal operation, theleakage current I_(LEAKAGE) of the I/O pad 5 is coincided with a currentat the crossing point between the graph of base current I_(PNP) and thegraph of sub-threshold current I_(PMOS).

In the ESD protection circuit of the embodiment, the operating point ismoved toward a direction where the leakage current I_(LEAKAGE) isreduced due to a voltage drop caused by the emitter-base voltage of PNPtransistor Q2. Although it is certain that a value of the emitter-basevoltage is slight (more typically, several tens mV), it may produce asubstantial effect in which the voltage drop caused by the emitter-basevoltage reduces the leakage current I_(LEAKAGE) because thesub-threshold current I_(PMOS) is decreased in a manner of exponentialfunction in respect to the gate-source voltage V_(GS). More practically,the leakage current I_(LEAKAGE) is reduced by one digit due to theemitter-base voltage of several tens mV. Test production and evaluationof the ESD protection circuit of the embodiment through CMOS process of65 nm showed that the leakage current of 10-13 (A) or less could berealized through application of the PMOS transistor 2 for a trigger withV_(STH) being 0.2 V.

Subsequently, a principle in which a trigger voltage when an ESD stressof positive voltage for the VSS pad 6 is applied to the I/O pad 5 isreduced will be described in reference to the configuration of the ESDprotection circuit of the embodiment. In regard to the case in which theESD stress of a positive voltage for the VSS pad 6 is applied to the I/Opad 5, it should be noticed that a potential of the VDD pad 4 is afloating one.

In reference to FIG. 6, when the ESD stress of a positive voltage forthe VSS pad 6 is applied to the I/O pad 5, the gate and the backgate ofthe PMOS transistor 2 for a trigger are also a floating one because thepotential of the VDD pad 4 is a floating one. Accordingly, the potentialof the I/O pad 5 required for making a state in which the PMOStransistor 2 for a trigger is ON (i.e. a state in which the gate-sourcevoltage V_(GS) of the PMOS transistor 2 for a trigger is lower than thethreshold voltage V_(TH)) is low. Accordingly, it is possible togenerate a trigger current I_(TRIG) by turning on the PMOS transistor 2for a trigger even with a low trigger voltage. Upon flowing of thetrigger current I_(TRIG), the SCR 1 starts to operate and the SCRcurrent I_(SCR) flows. The SCR current I_(SCR) flows into the VSS pad 6through the SCR 1. With this operation, an electrical load accumulatedin the I/O pad 5 is electrically discharged to the VSS pad 6.

Although current I_(INT) also flows into the VDD power supply line 21through a parasitic diode between the source and the backgate of thePMOS transistor 2 for a trigger, this current I_(INT) does not preventthe PMOS transistor 2 from being turned on and starting an operation ofthe SCR 1. Since the VDD power supply line 21 connected to the internalcircuit 8 has a sufficient capacity, a state in which the gate-sourcevoltage V_(GS) is lower than the threshold voltage V_(TH) is kept untilthe VDD power source line 21 is charged up, and then the channel currentof the PMOS transistor 2 for a trigger is continued to flow.

Since channel current in the PMOS transistor 2 for a trigger becomes atrigger current I_(TRIG) of the SCR 1, a trigger voltage of the SCR 1 isdetermined by dimensions of the PMOS transistor 2 for a trigger (i.e. agate length L and a gate width W), a film thickness T_(OX) and thethreshold voltage V_(TH) of the PMOS transistor 2 for a trigger. In thiscase, the threshold voltage V_(TH) is defined as a gate-source voltageV_(GS) when the drain-source current I_(DS) shows a value of −1 μA. As aresult of test manufacturing and evaluation of the ESD protectioncircuit of the embodiment through a 65 nm CMOS process, the triggervoltage of the SCR 1 could be reduced down to 1.8V under the followingconditions.

L=0.2 (μm)

W=10 (μm)

T_(OX)=1.3 (nm)

V _(TH)=−0.2 (V)

In addition, the ESD protection circuit of the embodiment also has anadvantage that it has also a low trigger voltage when the ESD stress ofa positive polarity for the VDD pad 4 is applied. FIG. 7 is a view forillustrating a principle where such advantage as above can be attained.In the case that the ESD stress of a positive polarity for the VDD pad 4is applied to the I/O pad 5, current flows from the I/O pad 5 to the VDDpower source line 21 through two forward diodes connected in series(i.e. emitter/base junction of PNP transistor Q2 and source-backgatejunction of the PMOS transistor 2 for a trigger). Accordingly, when itdoes not depend on the structure of the PMOS transistor 2 for a triggerand a potential of about 1.5 V (=approximately 0.7 V×2) of potential offorward bias of the two series-connected diodes occurs between the I/Opad 5 and the VDD pad 4, the trigger current I_(TRIG) flows. Uponflowing of the trigger current I_(TRIG), the SCR 1 starts to operate andthe SCR current I_(SCR) flows. The SCR current I_(SCR) flows into theVDD pad 4 through the SCR 1 and the power clamp diode 7. With thisoperation, the electrical load accumulated in the I/O pad 5 isdischargcd to the VDD pad 4. Actually, test production and evaluation ofthe ESD protection circuit of the embodiment through a 65 nm CMOSprocess enabled the trigger voltage of the SCR 1 to be reduced down to1.5V without being dependent on the structure of the PMOS transistor 2for a trigger. This value is a value that cannot be obtained by therelated art ESD protection circuit shown in FIGS. 1, 2 and 3.

Second Embodiment

FIG. 8A is a circuit diagram for showing a configuration of the ESDprotection circuit of a second embodiment of the present invention. Inthis embodiment, the PMOS transistor is not used, but the NMOStransistor is used as a trigger element for triggering the SCR. Alongwith this usage, a connecting relation among the SCR, pad and triggerelement is changed from that of the first embodiment.

More practically, the ESD protection circuit of the second embodimentcomprises an N-gate type SCR 1, the NMOS transistor 2A for a trigger,and a backward diode 3. The anode of the SCR 1 is connected to the VDDpad 4 and its cathode is connected to the I/O pad 5. The gate of the SCR1 is connected to the drain of the NMOS transistor 2A for a trigger. Thesource of the NMOS transistor 2A for a trigger is connected to the I/Opad 5 and its gate and backgate are connected to the VSS pad 6.

FIG. 8B is a sectional view for showing a connected relation among theSCR 1 and each of the pads 4 to 6. The P⁺ region 13 formed at the p-typesubstrate 11 is connected to the VSS pad 6 and the N⁺ region 14 isconnected to the I/O pad 5. The N⁺ region 14 may act as the cathode forthe SCR 1. The P⁺ region 15 formed at the N-well 12 is connected to theVDD pad 4 and the N⁺ region 16 is connected to the drain of the NMOStransistor 2A for a trigger. The P⁺ region 15 may act as an anode forthe SCR 1 and the N⁺ region 16 may act as a gate for it.

According to the configurations shown in FIG. 8A and FIG. 8B, it ispossible to reduce a trigger voltage when the ESD stress of a negativepolarity for the VDD pad 4 is applied to the I/O pad 5 due to the samereasons as that for the ESD protection circuit of the first embodiment.For a detail, since the VSS pad 6 is of a floating condition, the gateand backgate of the NMOS transistor 2A for a trigger are also of afloating condition. Thus, an amplitude of the ESD stress of negativepolarity required for making a state in which NMOS transistor 2A for atrigger is turned on (i.e. the gate-source voltage V_(GS) ecomes higherthan the threshold voltage V_(TH)) is low. Accordingly, the ESDprotection circuit of the second embodiment enables a trigger voltagewhen the ESD stress of negative polarity for the VDD pad 4 is applied tothe I/O pad 5 to be lowered.

In addition, the ESD protection circuit of the second embodiment enablesthe leakage current in the ESD protection circuit to be reduced due tothe same principle as that of the first embodiment by defining arestriction in which a signal level of a signal inputted or outputtedfor the I/O pad 5 is always higher than the ground level VSS (i.e. “Low”level of a signal inputted or outputted for the I/O pad 5 is defined asa predetermined potential higher than the ground level VSS). For moredetails, according to such an operation as above, since the VSS pad 6 iskept at the ground level VSS during normal operation, the gate and thebackgate of the NMOS transistor 2A for a trigger are also kept at theground level VSS. In turn, since the I/O pad 5 is always kept at ahigher potential than the ground level VSS, the source of the NMOStransistor 2 for a trigger is kept at a higher potential than the groundlevel VSS. Accordingly, the gate-source voltage V_(GS) of the NMOS for atrigger becomes a negative voltage. Since a threshold current of theNMOS transistor 2A for a trigger becomes quite low if the gate-sourcevoltage V_(GS) is negative, the leakage current in the ESD protectioncircuit becomes quite low. In this way, the ESD protection circuit ofthe second embodiment can reduce the leakage current in the ESDprotection circuit by properly operating the semiconductor integratedcircuit.

Although the embodiments of the present invention have been described invarious manners, it should not be interpreted that the present inventionis restricted to the above-mentioned embodiments. In particular,although the configuration having P⁺ region 13 and N⁺ region formed inthe P-type substrate 11 has been indicated, it is also possible to causeP⁺ region 13 and N⁺ region 14 to be formed into P-wells. In this case,the P-wells are formed to be connected adjacent to the N-well 12.

Further, it is noted that, Applicant's intent is to encompassequivalents of all claim elements, even if amended later duringprosecution.

1. A semiconductor circuit comprising: a first pad for a first powersource; a second pad for a second power source; a third pad for aninput/output signal; a protection element arranged between the first padand the third pad; and a transistor functioning as a trigger element foruse in passing a trigger current through the protection element, saidtransistor including a source connected to the third pad, a gate and abackgate commonly connected to the second pad.
 2. The semiconductorcircuit according to claim 1,wherein the protection element comprises asilicon controlled rectifier (SCR), wherein an anode of the SCR isconnected to the first pad, wherein a cathode of the SCR is connected tothe third pad, andwherein a gate of the SCR is connected to a drain ofthe transistor.
 3. The semiconductor circuit according to claim 2,wherein the SCR comprises: a member of a P-type substrate or a P-well; afirst P³⁺ region formed at the member and connected to the second pad; afirst N⁺ region formed at the member and connected to the third pad; anN-well formed at the P-type substrate or adjacent to the P-well; asecond P⁺ region formed at the N-well and connected to the first pad;and a second N⁺ region formed at the N-well and connected to a drain ofthe transistor.
 4. The semiconductor circuit as claimed in claim 1,wherein said transistor comprises a NMOS transistor, said first powersource comprises VDD, and said second power source comprises VSS.
 5. Thesemiconductor circuit as claimed in claim 1, wherein said second pad isat a ground level, the first pad is at a power supply voltage level, andsaid third pad is supplied with a signal always higher than the groundlevel.